View CY28441_4208462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CY28441
Clock Generator for Intel Alviso Chipset
Features
* Compliant to Intel CK410M * Supports Intel Pentium(R)-M CPU * Selectable CPU frequencies * Differential CPU clock pairs * 100 MHz differential SRC clocks * 96 MHz differential dot clock * 48 MHz USB clocks * SRC clocks independently stoppable through CLKREQ#[A:B] CPU x2 / x3 SRC x6 / x7 PCI x6 REF x1 DOT96 x1 USB_48 x1 * 33 MHz PCI clock * Low-voltage frequency select input * I2C support with readback capabilities * Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction * 3.3V power supply * 56-pin TSSOP package
Block Diagram
XIN XOUT CPU_STP# PCI_STP# CLKREQ[A:B]# FS_[C:A] VTT_PWRGD# IREF
Pin Configuration
VDD_PCI VSS_PCI PCI3 VDD_CPU PCI4 CPUT[0:1], CPUC[0:1], CPU(T/C)2_ITP] PCI5 VDD_SRC VSS_PCI SRCT[0:5], SRCC[0:5] VDD_PCI PCIF0/ITP_EN PCIF1 VTT_PWRGD#/PD VDD_PCI VDD_48 PCI[2:5] USB_48/FS_A VDD_PCIF VSS_48 PCIF[0:1] DOT96T DOT96C VDD_48 MHz FS_B/TEST_MODE DOT96T SRCT0 DOT96C SRCC0 USB_48 SRCT1 SRCC1 VDD_SRC SRCT2 SRCC2 SRCT3 SRCC3 SRC4_SATAT SRC4_SATAC VDD_SRC
VDD_REF REF
XTAL OSC PLL1
PLL Ref Freq
Divider Network
PD
PLL2
SDATA SCLK
I2C Logic
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
PCI2 PCI_STP# CPU_STP# FS_C/TEST_SEL REF VSS_REF XIN XOUT VDD_REF SDATA SCLK VSS_CPU CPUT0 CPUC0 VDD_CPU CPUT1 CPUC1 IREF VSSA VDDA CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 VDD_SRC CLKREQA# CLKREQB# SRCT5 SRCC5 VSS_SRC
56 TSSOP
CY28441
Rev 1.0, November 21, 2006
2200 Laurelwood Road, Santa Clara, CA 95054 Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 19
www.SpectraLinear.com
CY28441
Pin Description
Pin No. 33, 32 Name CLKREQA#, CLKREQB#, CPU_STP# CPUT2_ITP/SRCT7, CPUC2_ITP/SRCC7 DOT96T, DOT96C FS_A/USB_48 FS_B/TEST_MODE Type I, PU Description 3.3V LVTTL input for enabling assigned SRC clock, active LOW. CLKREQA# defaults to enable/disable SRCT/C4, CLKREQB# defaults to enable/disable SRCT/C5. Assignment can be changed via SMBUS register Byte 8. 3.3V LVTTL input for CPU_STP# active LOW.
54 36, 35
I, PU
44, 43, 41, 40 CPUT/C
O, DIF Differential CPU clock outputs. O, DIF Selectable differential CPU or SRC clock output. ITP_EN = 0 @ VTT_PWRGD# assertion = SRC7 ITP_EN = 1 @ VTT_PWRGD# assertion = CPU2 O, DIF Fixed 96-MHz clock output. I/O, SE 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. I 3.3V-tolerant input for CPU frequency selection. Selects Ref/N or Hi-Z when in test mode 0 = Hi-Z, 1 = Ref/N Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. 3.3V-tolerant input for CPU frequency selection. Selects test mode if pulled to greater than 2.0V when VTT_PWRGD# is asserted low. Refer to DC Electrical Specifications table for VIL_FS,VIH_FS specifications. A precision resistor is attached to this pin, which is connected to the internal current reference. 3.3V LVTTL input for PCI_STP# active LOW.
14, 15 12 16
53
FS_C/TEST_SEL
I
39 56, 3, 4, 5 55 8 9 52 46 47 26, 27
IREF PCI PCI_STP# PCIF0/ITP_EN PCIF1 REF SCLK SDATA SRC4_SATAT, SRC4_SATAC
I
O, SE 33 MHz clocks. I, PU I/O, SE 33-MHz clock/CPU2 select (sampled on the VTT_PWRGD# assertion). 1 = CPU2_ITP, 0 = SRC7 O, SE 33 MHz clock. O, SE Reference clock. 3.3V 14.318-MHz clock output. I I/O SMBus-compatible SCLOCK. SMBus-compatible SDATA.
O, DIF Differential serial reference clock. Recommended output for SATA. O, DIF Differential serial reference clocks.
SRCT/C 24, 25, 22, 23, 19, 20, 17, 18, 31, 30 11 42 1,7 48 21, 28, 34 37 13 45 2,6 51 29 38 10 VDD_48 VDD_CPU VDD_PCI VDD_REF VDD_SRC VDDA VSS_48 VSS_CPU VSS_PCI VSS_REF VSS_SRC VSSA VTT_PWRGD#/PD
PWR PWR PWR PWR PWR PWR GND GND GND GND GND GND I
3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for outputs. 3.3V power supply for PLL. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for outputs. Ground for PLL. 3.3V LVTTL input is a level sensitive strobe used to latch the USB_48/FS_A, FS_B, FS_C/TEST_SEL and PCIF0/ITP_EN inputs. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH).
Rev 1.0, November 21, 2006
Page 2 of 19
CY28441
Pin Description
Pin No. 50 49 XIN XOUT Name Type I 14.318-MHz crystal input. O, SE 14.318-MHz crystal output. initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Description
Frequency Select Pins (FS_A, FS_B and FS_C)
Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled LOW by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B and FS_C input values. For all logic levels of FS_A, FS_B and FS_C, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B and FS_C transitions will be ignored, except in test mode. See Table 1.
Data Protocol
The clock driver serial protocol accepts Byte Write, Byte Read, Block Write, and Block Read operations from the controller. For Block Write/Read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For Byte Write and Byte Read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The Block Write and Block Read protocol is outlined in Table 3 while Table 4 outlines the corresponding Byte Write and Byte Read protocol. The slave receiver address is 11010010 (D2h).
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 1. Frequency Select Table FS_A, FS_B and FS_C FS_C 1 0 0 0 0 1 1 1 FS_B 0 0 1 1 0 0 1 1 FS_A 1 1 1 0 0 0 0 1 CPU 100 MHz 133 MHz SRC 100 MHz 100 MHz
PCIF/PCI 33 MHz 33 MHz
REF0 14.318 MHz 14.318 MHz
DOT96 96 MHz 96 MHz
USB 48 MHz 48 MHz
RESERVED
Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block Read or Block Write operation, 1 = Byte Read or Byte Write operation Byte offset for Byte Read or Byte Write operation. For Block Read or Block Write operations, these bits should be '0000000'
Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Description Bit 1 8:2 9 10 18:11 19 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Block Read Protocol Description
Rev 1.0, November 21, 2006
Page 3 of 19
CY28441
Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 27:20 28 36:29 37 45:38 46 .... .... .... .... Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N -8 bits Acknowledge from slave Stop Description Bit 20 27:21 28 29 37:30 38 46:39 47 55:48 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Data byte - 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address - 7 bits Write Acknowledge from slave Command Code - 8 bits Acknowledge from slave Repeated start Slave address - 7 bits Read Acknowledge from slave Data from slave - 8 bits NOT Acknowledge Stop Byte Read Protocol Description Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte Count from slave - 8 bits Acknowledge Data byte 1 from slave - 8 bits Acknowledge Data byte 2 from slave - 8 bits Acknowledge Data bytes from slave / Acknowledge Data Byte N from slave - 8 bits NOT Acknowledge Stop Block Read Protocol Description
Control Registers
Byte 0:Control Register 0 Bit 7 6 5 4 3 @Pup 1 1 1 1 1 Name CPUT2_ITP/SRCT7 CPUC2_ITP/SRCC7 RESERVED SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 Description CPU[T/C]2_ITP/SRC[T/C]7 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable
Rev 1.0, November 21, 2006
Page 4 of 19
CY28441
Byte 0:Control Register 0 (continued) Bit 2 1 0 @Pup 1 1 1 Name SRC[T/C]2 SRC[T/C]1 SRC[T/C]0 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Description
Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 1 1 0 Name PCIF0 DOT_96T/C USB_48 REF Reserved CPU[T/C]1 CPU[T/C]0 CPUT/C SRCT/C PCIF PCI PCIF0 Output Enable 0 = Disabled, 1 = Enabled DOT_96 MHz Output Enable 0 = Disable (Hi-Z), 1 = Enabled USB_48 MHz Output Enable 0 = Disabled, 1 = Enabled REF Output Enable 0 = Disabled, 1 = Enabled Reserved CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enabled Spread Spectrum Enable 0 = Spread off, 1 = Spread on Description
Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 PCI Reserved Reserved PCIF1 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled PCI Output Drive strength 0 = Low drive 1 = High drive Reserved, Set = 1 Reserved, Set = 1 PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description
Byte 3: Control Register 3 Bit 7 6 5 @Pup 0 0 0 Name SRC7 RESERVED SRC5 Description Allow control of SRC[T/C]7 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP#
Rev 1.0, November 21, 2006
Page 5 of 19
CY28441
Byte 3: Control Register 3 (continued) Bit 4 3 2 1 0 @Pup 0 0 0 0 0 Name SRC4 SRC3 SRC2 SRC1 SRC0 Description Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]0 with assertion of PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP#
Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 1 1 1 Name Reserved DOT96T/C Reserved PCIF1 PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Reserved, Set = 0 DOT_PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Hi-Z Reserved, Set = 0 Allow control of PCIF1 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Description
Byte 5: Control Register 5 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name SRC[T/C][7:0] CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 SRC[T/C][7:0] CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted,1 = Hi-Z when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted,1 = Hi-Z when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted,1 = Hi-Z when PD asserted
Rev 1.0, November 21, 2006
Page 6 of 19
CY28441
Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 0 1 1 Reserved REF PCIF, SRC, PCI Name REF/N or Hi-Z Select 0 = Hi-Z, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Hi-Z mode, Reserved, Set = 0 REF Output Drive Strength 0 = 1X, 1 = 2X SW PCI_STP Function 0=SW PCI_STP assert, 1= SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will resume in a synchronous manner with no short pulses. FS_C Reflects the value of the FS_C pin sampled on power up 0 = FS_C was low during VTT_PWRGD# assertion FS_B Reflects the value of the FS_B pin sampled on power up 0 = FS_B was low during VTT_PWRGD# assertion FS_A Reflects the value of the FS_A pin sampled on power up 0 = FS_A was low during VTT_PWRGD# assertion Description
2 1 0
Externally selected Externally selected Externally selected
CPUT/C CPUT/C CPUT/C
Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description
BYTE 8: CLKREQ Control Register Bit 7 6 @Pup 0 1 Reserved CLKREQ#B Name Reserved SRC[T/C]5 CLKREQ#B control 1 = SRC[T/C]5 stoppable by CLKREQ#B pin 0 = SRC[T/C]5 not controlled by CLKREQ#B pin SRC[T/C]3 CLKREQ#B control 1 = SRC[T/C]3 stoppable by CLKREQ#B pin 0 = SRC[T/C]3 not controlled by CLKREQ#B pin SRC[T/C]1 CLKREQ#B control 1 = SRC[T/C]1 stoppable by CLKREQ#B pin 0 = SRC[T/C]1 not controlled by CLKREQ#B pin Reserved SRC[T/C]4 CLKREQ#A control 1 = SRC[T/C]4 stoppable by CLKREQ#A pin 0 = SRC[T/C]4 not controlled by CLKREQ#A pin SRC[T/C]2 CLKREQ#A control 1 = SRC[T/C]2 stoppable by CLKREQ#A pin 0 = SRC[T/C]2 not controlled by CLKREQ#A pin Description
5
0
CLKREQ#B
4
0
CLKREQ#B
3 2
0 1
Reserved CLKREQ#A
1
0
CLKREQ#A
Rev 1.0, November 21, 2006
Page 7 of 19
CY28441
BYTE 8: CLKREQ Control Register Bit 0 @Pup 0 Name CLKREQ#A Description SRC[T/C]0 CLKREQ#A control 1 = SRC[T/C]0 stoppable by CLKREQ#A pin 0 = SRC[T/C]0 not controlled by CLKREQ#A pin
Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm
Crystal Recommendations
Clock Chip
The CY28441 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28441 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. See Table 5.
Ci1
Ci2 Pin 3 to 6p
Crystal Loading
Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It's a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true.
Cs1 X1 X2 Cs2 Trace 2.8pF XTAL Ce1
Ce2
Trim 33pF
Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side)
Figure 1. Crystal Capacitive Clarification
Ce = 2 * CL - (Cs + Ci) Total Capacitance (as seen by the crystal) CLe
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides.
=
1 ( Ce1 + Cs1 + Ci1 +
1
1 Ce2 + Cs2 + Ci2
)
CL....................................................Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce..................................................... External trim capacitors Cs .............................................. Stray capacitance (terraced) Ci ...........................................................Internal capacitance (lead frame, bond wires etc.)
Rev 1.0, November 21, 2006
Page 8 of 19
CY28441
CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active LOW input used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that it's state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and deassertion of this signal is absolutely asynchronous.)
.
CLKREQ#X
SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable)
Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2-6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs will be driven HIGH within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) - Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next HIGH to LOW transition and differential clocks must held HIGH or Hi-Zd (depending on the state of the control register drive mode bit) on the next diff clock# HIGH to LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to `0', the clock output are held with "Diff clock" pin driven HIGH at 2 x Iref, and "Diff clock#" tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to "1", then both the "Diff clock" and the "Diff clock#" are tristate. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = `1' for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100 and 133 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted HIGH in less than 10 s after asserting Vtt_PwrGd#.
Rev 1.0, November 21, 2006
Page 9 of 19
CY28441
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF
Figure 4. Power-down Assertion Timing Waveform
Tstable <1.8nS
PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33MHz REF
Tdrive_PWRDN# <300 S, >200mV
Figure 5. Power-down Deassertion Timing Waveform PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 s of PD deassertion to a voltage greater than 200 mV. After the clock chip's internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. CPU_STP# Assertion The CPU_STP# signal is an active LOW input used for synchronous stopping and starting the CPU output clocks while the rest of the clock generator continues to function. When the CPU_STP# pin is asserted, all CPU outputs that are set with the SMBus configuration to be stoppable via assertion of CPU_STP# will be stopped within two-six CPU clock periods after being sampled by two rising edges of the internal CPUC clock. The final states of the stopped CPU signals are CPUT = HIGH and CPUC = LOW. There is no change to the output drive current values during the stopped state. The CPUT is driven HIGH with a current value equal to 6 x (Iref), and the CPUC signal will be Hi-Z
Rev 1.0, November 21, 2006
Page 10 of 19
CY28441
.
CPU_STP#
CPUT CPUC
Figure 6. CPU_STP# Assertion Waveform CPU_STP# Deassertion The deassertion of the CPU_STP# signal will cause all CPU outputs that were stopped to resume normal operation in a synchronous manner. Synchronous manner meaning that no
CPU_STP# CPUT CPUC CPUT Internal CPUC Internal
Tdrive_CPU_STP#,10nS>200mV
short or stretched clock pulses will be produce when the clock resumes. The maximum latency from the deassertion to active outputs is no more than two CPU clock cycles.
Figure 7. CPU_STP# Deassertion Waveform
1.8mS CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable)
DOT96T DOT96C
Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven
Rev 1.0, November 21, 2006
Page 11 of 19
CY28441
1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable)
DOT96T DOT96C
Figure 9. CPU_STP# = Hi-Z, CPU_PD = Hi-Z, DOT_PD = tHi-Z PCI_STP# Assertion[1] The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running.
Tsu
PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a high level. (See Figure 11.)
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 10. PCI_STP# Assertion Waveform
Tsu Tdrive_SRC
PCI_STP# PCI_F
PCI SRC 100MHz
Figure 11. PCI_STP# Deassertion Waveform
Note: 1. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 55 and the other is SMBus byte6 bit 3. These two inputs are logically OR'ed. If either the external pin or the internal SMBus register bit is set LOW then the stoppable PCI clocks will be stopped in a logic LOW state.
Rev 1.0, November 21, 2006
Page 12 of 19
CY28441
FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM
VDD Clock Gen Clock State State 0
0.2-0.3mS Delay State 1
W ait for VTT_PW RGD#
Sample Sels State 2 State 3
Device is not affected, VTT_PW RGD# is ignored
Clock Outputs
Off
On
Clock VCO
Off
On
Figure 12. VTT_PWRGD# Timing Diagram
S1
S2 VTT_PWRGD# = Low
Delay >0.25mS
VDD_A = 2.0V
Sample Inputs straps
Wait for <1.8ms S0 S3 VDD_A = off
Power Off
Normal Operation
VTT_PWRGD# = toggle
Enable Outputs
Figure 13. Clock Generator Power-up/Run State Diagram
Rev 1.0, November 21, 2006
Page 13 of 19
CY28441
Absolute Maximum Conditions
Parameter VDD VDD_A VIN TS TA TJ OJC OJA ESDHBM UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Non-functional Functional Functional Mil-STD-883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - - - 2000 V-0 1 Max. 4.6 4.6 VDD + 0.5 150 85 150 39.56 45.29 - Unit V V VDC C C C C/W C/W V
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter Description 3.3 5% Condition Min. 3.135 Max. 3.465 Unit V VDD_A, 3.3V Operating Voltage VDD_REF, VDD_PCI, VDD_3V66, VDD_48, VDD_CPU VILI2C VIHI2C VIL_FS VIH_FS VIL VIH IIL IIH VOL VOH IOZ CIN COUT LIN VXIH VXIL IDD3.3V IPD3.3V IPD3.3V Input Low Voltage Input High Voltage FS_A/FS_B/FS_C Input Low Voltage FS_A/FS_B/FS_C Input High Voltage 3.3V Input Low Voltage 3.3V Input High Voltage Input Low Leakage Current Input High Leakage Current 3.3V Output Low Voltage 3.3V Output High Voltage High-impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current Power-down Supply Current At max. load and freq. per Figure 15 PD asserted, Outputs driven PD asserted, Outputs Hi-Z Except internal pull-up resistors, 0 < VIN < VDD Except internal pull-down resistors, 0 < VIN < VDD IOL = 1 mA IOH = -1 mA
SDATA, SCLK SDATA, SCLK
- 2.2 VSS - 0.3 0.7 VSS - 0.5 2.0 -5 - - 2.4 -10 2 3 - 0.7VDD 0 - - -
1.0 - 0.35 VDD + 0.5 0.8 VDD + 0.5 - 5 0.4 - 10 5 6 7 VDD 0.3VDD 380 70 2
V V V V V V A A V V A pF pF nH V V mA mA mA
Rev 1.0, November 21, 2006
Page 14 of 19
CY28441
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70 but the REF clock duty cycle will not be within specification When XIN is driven from an external clock source Measured between 0.3VDD and 0.7VDD As an average over 1- s duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Min. 47.5 Max. 52.5 Unit %
TPERIOD T R / TF TCCJ LACC CPU at 0.7V TDC TPERIOD TPERIOD TPERIODSS TPERIODSS TPERIODAbs TPERIODAbs
XIN Period XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CPUT and CPUC Duty Cycle 100-MHz CPUT and CPUC Period 133-MHz CPUT and CPUC Period
69.841 - - - 45 9.997001 7.497751 9.997001 7.497751 9.912001 7.412751 9.912001 7.412751 - - - - 175 - - -
71.0 10.0 500 300 55 10.00300 7.502251 10.05327 7.539950 10.08800 7.587251 10.13827 7.624950 125 125 100 150 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 10.00300 10.05327 9.872001 10.17827
ns ns ps ppm % ns ns ns ns ns ns ns ns ps ps ps ps ps % ps ps mV mV mV V V V % ns ns ns ns
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX 100-MHz CPUT and CPUC Absolute Period 133-MHz CPUT and CPUC Absolute Period Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF)
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute Period, SSC TPERIODSSAbs 133-MHz CPUT and CPUC Absolute Period, SSC TCCJ TCCJ2 TSKEW TSKEW2 T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB SRC TDC TPERIOD TPERIODSS TPERIODAbs CPUT/C Cycle to Cycle Jitter CPU2_ITP Cycle to Cycle Jitter CPUT to CPUC Clock Skew CPU2_ITP to CPU0 Clock Skew CPUT and CPUC Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage SRCT and SRCC Duty Cycle 100-MHz SRCT and SRCC Period 100-MHz SRCT and SRCC Absolute Period
Math averages Figure 15 Math averages Figure 15
660 -150 250 - -0.3
See Figure 15. Measure SE Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX
- 45 9.997001 9.997001 10.12800 9.872001
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute Period, SSC
Rev 1.0, November 21, 2006
Page 15 of 19
CY28441
AC Electrical Specifications (continued)
Parameter TSKEW TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB PCI/PCIF TDC TPERIOD TPERIODSS TPERIODAbs THIGH TLOW T R / TF TSKEW TCCJ DOT TDC TPERIOD TPERIODAbs TCCJ LACC T R / TF TRFM TR TF VHIGH VLOW VOX VOVS VUDS VRB Description Any SRCT/C to SRCT/C Clock Skew SRCT/C Cycle to Cycle Jitter SRCT/C Long Term Accuracy SRCT and SRCC Rise and Fall Times Rise/Fall Matching Rise TimeVariation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage PCI Duty Cycle Spread Disabled PCIF/PCI Period Spread Disabled PCIF/PCI Period PCIF and PCI High Time PCIF and PCI Low Time PCIF and PCI Rise and Fall Times Any PCI clock to Any PCI Clock Skew PCIF and PCI Cycle to Cycle Jitter DOT96T and DOT96C Duty Cycle DOT96T and DOT96C Period DOT96T/C Cycle to Cycle Jitter DOT96T/C Long Term Accuracy DOT96T and DOT96C Rise and Fall Times Rise/Fall Matching Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage See Figure 15. Measure SE Math averages Figure 15 Math averages Figure 15 See Figure 15. Measure SE Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Math averages Figure 15 Math averages Figure 15 Condition Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured from VOL = 0.175 to VOH = 0.525V Determined as a fraction of 2*(TR - TF)/(TR + TF) Min. - - - 175 - - - 660 -150 250 - -0.3 - 45 29.99100 29.9910 29.49100 29.49100 12.0 12.0 0.5 - - 45 10.41354 10.16354 - - 175 - - - 660 -150 250 - -0.3 - Max. 250 125 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 55 30.00900 30.15980 30.50900 30.65980 - - 2.0 500 500 55 10.41979 10.66979 250 300 700 20 125 125 850 - 550 VHIGH + 0.3 - 0.2 Unit ps ps ppm ps % ps ps mV mV mV V V V % ns ns ns ns ns ns ns ps ps % ns ns ps ppm ps % ps ps mV mV mV V V V
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
Rev 1.0, November 21, 2006
Page 16 of 19
CY28441
AC Electrical Specifications (continued)
Parameter TLTJ USB TDC TPERIOD TPERIODAbs THIGH TLOW T R / TF TCCJ REF TDC TPERIOD TPERIODAbs T R / TF TCCJ Description Long Term Jitter @ 10 s Duty Cycle Period Absolute Period USB High Time USB Low Time Rise and Fall Times Cycle to Cycle Jitter REF Duty Cycle REF Period REF Absolute Period REF Rise and Fall Times REF Cycle to Cycle Jitter Condition Measured at crossing point VOX Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 2.4V Measurement at 0.4V Measured between 0.8V and 2.0V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.8V and 2.0V Measurement at 1.5V 45 20.83125 20.48125 8.094 7.694 1.0 - 45 69.8203 68.82033 0.5 - - 10.0 0 Min. Max. 1.1 55 20.83542 21.18542 10.036 9.836 2.0 350 55 69.8622 70.86224 2.0 1000 1.8 - - Unit ns % ns ns ns ns ns ps % ns ns V/ns ps ms ns ns
ENABLE/DISABLE and SET-UP TSTABLE Clock Stabilization from Power-up TSS TSH Stopclock Set-up Time Stopclock Hold Time
Test and Measurement Set-up
The following diagram shows the test load configurations for the single-ended USB, and REF output signals
USB
5pF
M e a s u re m e n t P o in t
M e a s u re m e n t P o in t
5pF
REF
M e a s u re m e n t P o in t
5pF
For PCI Single-ended Signals and Reference Figure 14 shows the test load configuration for single-ended PCI outputs.
Rev 1.0, November 21, 2006
Page 17 of 19
CY28441
tDC 3.3V 2.4V 1.5V 0.4V 0V T r T f Figure 14. Single-ended Lumped Load Configuration for PCI Outputs Load Cap 30pF Output under Test P robe
For Differential CPU, SRC and DOT96 Output Signals Figure 15 shows the test load configuration for the differential CPU and SRC outputs.
CPUT SRCT D O T96T CPUC SRCC D O T96C IR E F
M e a s u re m e n t P o in t
2pF
D if f e r e n t ia l
M e a s u re m e n t P o in t
2pF
Figure 15. 0.7V Single-ended Load Configuration
3 .3 V s ig n a l s
T DC
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V 0V
TR
TF
Figure 16. Single-ended Output Signals (for AC Parameters Measurement)
Rev 1.0, November 21, 2006
Page 18 of 19
CY28441
Ordering Information
Part Number Lead-free Package Type Product Flow
CY28441ZXC CY28441ZXCT
56-pin TSSOP 56-pin TSSOP - Tape and Reel
Commercial, 0 to 85 C Commercial, 0 to 85 C
Package Drawing and Dimensions
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547] 14.097[0.555]
1.100[0.043] MAX.
GAUGE PLANE 0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008]
0.170[0.006] 0.279[0.011]
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any circuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other application requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any circuitry or specification without notice.
Rev 1.0, November 21, 2006
Page 19 of 19

▲Up To Search▲

Price & Availability of CY28441

	To Download CY28441 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .